The present invention relates to an information processing apparatus having a hierarchical memory structure and a direct memory access (DMA) function. More specifically, the invention is applied to an information processing apparatus in which integrity between hierarchized memories (e.g., between a main memory and a cache memory) is guaranteed by a snoop process when a DMA occurs.
In order to allow a CPU of an information processing apparatus to access memories at high speed, an information processing apparatus having a hierarchical memory structure of a cache memory and a main memory are becoming a main trend.
With a hierarchical memory structure, it is not necessary for CPU to access the main memory every time. From this reason, incorporation of a DMA control scheme is also becoming a main trend, by which scheme an I/O device or the like directly access the main memory while CPU is not accessing the main memory.
In realizing the DMA control scheme in an information processing apparatus having a hierarchical memory structure, it is necessary for a DMA process to execute data transfer between the main memory and the cache memory after integrity between data in the main memory and the cache memory is confirmed. Therefore, when a DMA occurs, a memory controller receiving DMA usually issues a snoop access request to the cache memory to confirm whether the cache memory has data or the like in the area indicated by a DMA address.
During this period, an access to the cache memory by a CPU is required to be temporarily suspended so that the system performance of the information processing apparatus lowers.
A conventional technique for solving this problem and improving the system performance is disclosed in JP-A-7-105086 xe2x80x9cBus Snoop Control Devicexe2x80x9d.
With this conventional technique, when a snoop process for a cache memory occurs, a previous snoop address and a current snoop address are compared. If the current search is directed to the same block, an unnecessary interrupt of CPU is not executed so that the performance of CPU can be improved by an amount corresponding to one interrupt process.
This conventional technique is applied to the system structure that a plurality of CPU boards having a cache memory and a CPU are connected to one system bus to which a main memory and I/O channel boards are also connected. A snoop detector circuit for comparing a previous snoop address and a current snoop address is provided on the same CPU board as the cache memory.
Therefore, if an I/O channel board executes a DMA to the main memory, the system bus is occupied by the snoop access to the cache memory in the CPU board and by the DMA to the main memory.
Although an unnecessary interrupt process for CPU is suppressed by the snoop process for the cache memory, the system bus itself is occupied by the DMA so that the CPU board cannot use this system bus. During this period, communications between CPUs and the like cannot use the system bus. Namely, there is a problem that improvement on the system performance through reduction of system bus traffics cannot be expected.
The present invention aims at solving the above-described problem.
It is an object of the present invention to provide an information processing apparatus whose system performance is improved through interruption of an access to a cache memory by a CPU and reduction of system bus traffics, in response to a snoop access request, to provide a memory controller to be used by such information processing apparatus and to provide a direct memory access processing method.
In order to achieve the above object, the present invention provides an information processing apparatus having a first bus of upper upper level (system bus) for interconnecting a central processing unit (CPU) and a cache memory, a second but (I/O bus) for interconnecting an I/O device, a main memory, and a memory controller connected to the first and second buses and main memory for controlling the main memory, wherein an address indicated by a direct memory access request issued by the I/O device is compared with the contents of a buffer memory in the memory controller, and if there is any coincidence, a snoop access process request is inhibited to be sent to the cache memory or to the first bus.
The buffer memory in the memory controller stores addresses used for past direct memory accesses, i.e., addresses used when snoop process requests were issued in the past.
If a DMA access is issued to an area for which a snoop access was executed previously and if data in the cache memory is not updated, integrity between the cache memory and main memory can be guaranteed. The memory controller connected to both buses of a double-bus structure has an inhibition circuit for a snoop process. Therefore, it is possible to execute a direct memory access by using only the I/O bus without affecting the upper upper bus.
According to the present invention, an unnecessary snoop process for the main memory can be eliminated. Therefore, the number of unnecessary interrupt processes for CPU can be reduced and occurrence frequencies that the upper hierarchical bus of the double-bus structure is occupied by unnecessary signals, can be reduced.
Accordingly, communications between circuits connected to the system bus are not obstructed and the system performance can be improved.
In embodying the present invention, the number of buffer levels of the buffer memory for storing DMA addresses is not limited to one stage, but a plurality of buffer levels may also be used to further reduce the number of chances of suppressing the snoop process.
The control method for a hierarchical memory structure to be used by a system embodying the present invention is effective for all hierarchical memory structures such as a write-back cache scheme, a write-through cache scheme and a combination thereof. The number of hierarchical bus levels and the bus specifications are also not limited.
In addition to the information processing apparatus, the invention discloses a novel memory controller to be used by the apparatus.
Specifically, the memory controller has connection means for connection to the upper and lower level buses, connection means for connection to the main memory, and the above-described suppression circuit for the DMA process.
A snoop process request output from the connection means on the upper level bus side is suppressed to shorten the time during which the upper level bus is occupied.